For past 10 days I m working on Accelerator redesign. Basic changes are related to voltage level translation because in previous versions voltage level translation was not complete. Using 74ALVT162245 devices, who have 5V tolerant I/O's, was not best solution because those devices can be only used in process of translation CMOS to LVCMOS but those devices was unusable to translate back LVCMOS to CMOS. In this case all of the signals coming from Amiga 600 board was readable by FPGA but signals going from FPGA to Amiga 600 board was unusable because those signals were never translated to CMOS because 74ALVT162245 is not real translator just transceiver who have 5V tolerant I/O's. Lot of people are talking that rest of Amiga hardware can work with LVCMOS signals but with this new design I just wanted to be shore that level translation isn't problem in design of this Accelerator board. So I decided to use dual supply translating transceiver, and yes like I said before I didn't use those devices because they can complicate design and drive to number of problems on 2 layer PCB. My choice was 74ALVC164245 and main difference here is that VCC(A) is tracking A side of the device and VCC(B) is tracking B side so if we use 5V on one and 3.3V on other side we have complete level translation between CMOS and LVCMOS and vice verse. Other changes on design are related to proper solving BR, BGACK, BG, RESET, HALT and some more signals. Those changes was needed because I may decide to have original CPU up and running for some time until FPGA takes over the bus. New series of devices are ordered, and PCB will be produced in next few days. Here is tracking number so you can track order if you want :) RC110182668HK