While working toward the first successful Kickstart boot, I also want to document the basic architecture of the Majsta 68K core. The current structure is intentionally different from something like TG68. Instead of implementing most CPU behavior inside one very large state machine, instructions are divided into separate functional owners. The basic flow is: Frontend → Decoder → Instruction Owners → Register/Commit → Memory Unit with a separate event/exception path handling interrupts and exceptions. At this stage this approach is not particularly efficient in FPGA resource usage. Many operations are still implemented directly in VHDL, and the separation between owners introduces logic that can later be simplified or shared. However, this architecture has been extremely useful during early development. Each instruction family can be developed and debugged relatively independently, and changes in one area are less likely to disturb unrelated instructions. A simple way to imagine the design is like water flowing through a pipe: instructions move from the frontend through decode, into the appropriate owner, and finally toward register commit or memory. The current design should therefore not be considered the final architecture. The plan after achieving a reliable boot is to keep the clean functional separation while reducing duplicated logic and FPGA resource usage. The second picture also shows how much the implementation has grown during the last months. For example, majsta_decode_pkg.vhd grew from roughly 18 KB to 172 KB as instruction coverage expanded. This is still very much an evolving CPU architecture, but the owner-based structure has made it possible to reach this stage.

Simplified Majsta 68K architecture during the September 2026 development stage: frontend, decoder, independent instruction owners, commit logic and memory unit.


The RTL had grown significantly as instruction coverage expanded; majsta_decode_pkg.vhd alone increased from about 18 KB from early 2025. to 172 KB now.