Theory of operation
Date: Wednesday, January 30 2013 @ 16:59:58 UTC
Topic: Amiga FPGA accelerator


Those days I m receiving lots of mails regarding real speed of this accelerator. Also, I have noticed lot of discussions about this on various forums. Somehow all of those testings was very confusing for most of the people especially when I published information's that I m able to run TG68 core at 127MHz and that I have done promising testings on 150 and 200Mhz. To understand why all of this is so slow we need to explain how Amiga accelerators work. And we can do it in just one sentence. Every CPU from MC68K series used to replace model used on motherboard needs to mimic his bus cycles and acceleration can be expected only when we connect some peripheral device to that new CPU. So like you can see at this point it is essential to create exact timings according to 7.09Mhz CPU clock and then add memory to new CPU at higher speed. This is the only way we can overcome "slow" bus timings regarding to original clock so those bus timings will be used only in situation when new CPU needs to talk to Amiga motherboard. Everything else will happen on much higher clock rate between new CPU and the added memory. For now I m just 0.06Mips behind original MC68K so few more tweaks needs to be done. After that, when we add memory we will know for shore is this an Accelerator or my complete theory was wrong.







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