Yes it was fastest Amiga 600 but somehow there are lot of problems with cache. Why? After few days of investigation I must say that I have no idea. I have tried everything from changing SDRAM chip to checking every single trace on the board. Problem here is that I just can't load all signals needed in SignalTapII to see what is wrong because this FPGA I m using is too small for that. So I m stuck with this now, error is somewhere between SDRAM controller and cache. So today I have managed to create simple SDRAM controller without cache to see can this design work at all. Controller works somehow but again system breaks at one point. So we will see once this controller works maybe we can find a reason for other problems. Yes there are few designs open sourced but it is hard to track what someone wanted to say in code. I know only one thing if I ever finish this project it will be because amazing help from robinson5 from retroramblings.net. So are we close, we were close 2 years ago but it seems that playing with electronics designs is hard :).